1. Field of the Invention
This invention relates to a structure of a trench contact structure of silicon on insulator (SOI), and more particular to a structure of a trench contact structure of SOI used in a Bipolar-Complementary-Metal-Oxide-Semiconductor (BiCMOS) device.
2. Description of Related Art
The technology of SOI is about a technology of isolation used in a complementary-metal-oxide-semiconductor (CMOS) device. Its characteristics is that an insulating layer, in general, made of silicon dioxide is formed closely under the surface of the substrate to isolate the CMOS device from the main silicon substrate. Therefore, because the CMOS area isn't connected to the substrate, latch-up happening on the transistors within the active area would disappear due to the routes causing latch-up such as source to subtrate or well to substrate having been disconnected by the insulating layer.
The SOI described in the above can be done by one of following methods like separation by implanted oxygen (SIMOX), bonded wafer (BW), or dielectric isolation (DI). The advantages of the technology of SOI in the fabrication of the integrated circuit is not only able to effectively restrain the happening of latch-up electrically on the CMOS transistors due to the parasitic bipolar effect but also able to increase the immunity of MOS device to the soft error induced by the at particles. In the fabricating procedures, due to the line width being allowed to be reduced, it would be easier for the fabrication and therefore the size of the parasitic capacitors and the device are reduced to be able to increase the speed of the operation of the circuit.
The idea of a BiCMOS device is to carry both bipolar transistors and CMOS transistors so that the parts of circuit needing the high speed of the operation and the high current such as the Input/Output (I/O) can be done by the bipolar transistors and the areas needing the high integration and the low consumption of power such as the array area can be made by the CMOS transistors.
A BiCMOS device is formed on a substrate, which carries the structure with SOI, and lets the gate of the CMOS transistor be electrically coupled to the base of the transistor, in that a low power-delay multiplier would be more efficient. To apply a low voltage on the gate of the CMOS transistor some area of the available area of the device is needed to make a contact window and to apply a low voltage on the substrate with SOI device an additional area is needed either. This would undermine the integration due to the consuming of the area.
FIG. 1 illustrates the top view of a scheme of a conventional BiCMOS device using the technology of SOI. Referring to FIG. 1 a substrate 100 has a structure of SOI, wherein a gate 102 of the MOS and the source/drain regions 104a, 104b are formed on the substrate 100. The gate 102 and the base 101 are interconnected to the metal layer 108 through the contact windows 106b and thus they are electrically coupled together. Moreover a doped area 110 on the substrate around the contact window 106b with the same type of dopant as used in the substrate but higher density is to give a better electrically coupled effect. The scheme as illustrated in the FIG. 1 has a few drawbacks that it increases the needed area of the device and results in the decrease of the integration and the complexity in the fabricating procedures.